Speaker(s):  Dr. Kiran Gunnam, Distinguished Lecturer, IEEE Solid-State Circuits Society, Director of Engineering at Violin Memory, Mountain View, CA
 Date/Time: Thursday, Sept. 5, 2013,, 2:30pm – 4pm
Location: MC2014, Carleton University
Parking: As per meter
Registration: Free
Organizer: Prof. Ram Achar
 Organizer e-mail: achar@doe.carleton.ca
 Organized by: IEEE Ottawa Section, and its Chapters: SSCS/ EDS/CASS Joint Chapter, ComSoc/BTS/CES Joint Chapter, SP/OE/GRS Joint Chapter, EMBS Chapter, CPMT Chapter and the IEEE Canada Eastern Area

Abstract: Part 1 of this lecture covers introduction to VLSI architectures for Communications and Signal Processing Systems. Various topics include pipelining and parallel processing, retiming, unfolding, folding, systolic architecture design and algorithmic transformations. The emphasis is how to design high-speed, low-area, and low-power VLSI systems for a broad range of DSP and communication applications.

Part 2 of this lecture covers speaker’s research. Low-Density Parity-Check codes now have been firmly established as coding technique for communication and storage channels. This talk gives an overview of the speaker’s research and contributions in the development of low complexity iterative LDPC solutions for Turbo Equalization for magnetic recording storage channels. Complexity is reduced by developing new or modified algorithms and new hardware architectures viz. system level hardware architecture, statistical buffer management and queuing, local-global inter-leaver, LDPC decoder and error floor mitigation schemes.