Challenges for Electronics Design in the Nano-Scale
Distinguished Lecturer, IEEE Circuits and Systems society,
Dept. of EECS, Northwestern University, Evanston, IL60208-3118
Refreshments: Served
Bio: Prof. Yehea Ismail is the director of the Nanoelectronics Center at Northwestern University and the AUC. The center was inaugurated by Craig Barrett, Intel’s chairman of the board in 2008, while in Nile University.
Professor Ismail is the Editor-in-Chief of the IEEE Transaction on Very Large Scale Integration (TVLSI) and the chair elect of the IEEE VLSI Technical Committee. He is on the editorial board of the Journal of Circuits, Systems, and Computers, was on the editorial board of the IEEE Transactions on Circuits and Systems I. Fundamental Theory and Applications, and a guest editor for a special issue of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems on “On-Chip Inductance in High Speed Integrated Circuitsâ€. He has also chaired many conferences such as GLSVLSI, IWSOC, ISCAS. He is the Chief Scientist of the Innovation and Entrepreneurship Center of the Ministry of Communications and Information Technology, Egypt.
Professor Ismail has several awards such as the USA National Science Foundation Career award, the IEEE CAS outstanding author award, Best teacher award at Northwestern University, many best paper awards and teaching awards. Professor Ismail is the distinguished lecturer of IEEE CASS. He is an IEEE Fellow.
Professor Ismail has published more than 170 papers in the top refereed journals and conferences and many patents. He co-authored three books: On-Chip Inductance in High Speed Integrated Circuits, Handbook on Algorithms for VLSI Physical Design, and Temperature-Aware Computer Architecture. He has many patents in the area of high performance circuit and interconnect design and modeling. His work
Semiconductor technologies exhibited explosive growth in complexity and speed over the last two decades. Since the early 1980s, the device sizes have scaled down from few micrometers to tens of Nano-meters and the operating frequencies have increased from a few megahertz to several gigahertz. Also, the spacing between devices and interconnect have dramatically decreased due to the continuous scaling down of the technology feature size. These trends have led to issues and challenges in the design and analysis of high performance integrated circuits that previous generations did not exhibit. Most of these issues are at the circuit and interconnect (physical) levels. Also, these issues are expected only to increase in importance in future generations of integrated circuits. This talk will overview the most important challenges for electronics design in the nano-scale.